D16's FPGA-Master 2.0 brings together iBasso's algorithm achievements from the past three years and is the reason we have been able to accomplish breakthroughs for our portable discrete DAC. FPGA plays the role of signal reorganization and recoding, which generates PWM signals that can be decoded by the subsequent PWM-DAC. DAC developers are well aware that when the THD reaches a certain level, the presence of noise becomes a hindrance to achieving a greater dynamic range. The D16's FPGA-Master2.0 boasts an impressive noise shaper that radically lowers the noise floor. Global clock regeneration technology is employed. Two Accusilicon femtosecond oscillators provide a clock reference for the FPGA. The FPGA regenerates the synchronous low-phase noise clock required by the DSP and USB receiver. 1bit DACs are very sensitive to clock jitter. We have tested a variety of femtosecond oscillators of various brands and Accusilicon's audio oscillator has a phase noise as low as -158dBc/Hz [@1kHz]. Compared with the -145dBc/Hz of a general femtosecond oscillator, the phase noise is reduced by 13dB, which guarantees excellent Jitter control for the D16. Picosecond-level precise delay control, which can set the I/O delay and compensate for the "wiring delay" of the board so that the signals arriving at the DAC end are aligned and strictly synchronized. With the precise control of FPGA-Master 2.0, 128 independent PWM-DACs operate in FIR mode and combine to form L+, L-, R+, R- outputs. Every DAC data bit undergoes careful delay and alignment through rigorous compensation.
After the FPGA generates the PWM signal, it arrives the discrete PWM-DAC for decoding. Employing 16 sets of an 8E PWM-DAC cascade. There are 4 sets per L+, L-, R+, R-, which is 32 PWM-DACs. The quantity of the DAC exceeds that of other portable discrete DACs by more than 6.4 times. With the exceptional combination of precise decoding and a substantial quantity of extremely high-quality DACs a THD+N level of less than 0.0001% is achieved and represents an exceptional performance.
With FPGA-Master2.0’s picosecond-level precise control, 128 independent PWM-DACs operate in FIR mode and combine to form L+, L-, R+, R- outputs. Each channel has 32 PWM-DACs operating in "delay parallel" mode. This configuration enables the 32 DACs to work together as a hardware analog FIR filter. By averaging the differences between multiple DACs, distortion is minimized, resulting in enhanced sound detail and density.
The D16 utilizes the similar architecture to the DX320MAX, a super Class A discrete AMP circuit. It incorporates 20pcs of Low VCEsat (BISS) dual transistors and boasts an impressive output current capability of up to 2A, resulting in a robust output of 1125mW+1125mW@32Ω.
1. 128pcs low-temperature drift 0.1% high-precision 25ppm thin film resistors.
2. 24 position 4 section stepped attenuator with a channel tolerance less than +/-0.1dB.
3. Dual Accusilicon ultra-low phase noise femtosecond oscillators, with a noise floor as low as -158dBc/Hz (@1kHz).
4. Professional audio DSP chip, theoretical dynamic range up to 192dB, THD+N up to -174dB.
5. Ultra-low noise analog power supply with noise as low as 0.6μV.
6. 1.3-inch OLED display